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Davicom公司DM9000A和DM9010ISANIC以太网驱动分析

发布时间:2020-07-21 17:48:09 阅读: 来源:邦定机厂家

/*

本文引用地址: Version 2.03 2005/10/17

A Davicom DM9000A/DM9010 ISA NIC fast Ethernet driver for Linux.

This program is free software; you can redistribute it and/or

modify it under the terms of the GNU General Public License

as published by the Free Software Foundation; either version 2

of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

GNU General Public License for more details.

(C)Copyright 1997-2005 DAVICOM Semiconductor,Inc. All Rights Reserved.

V1.00 10/13/2004 Add new function Early transmit IP/TCP/UDP Checksum

offload enable flow control is default

V1.1 12/29/2004 Add Two packet mode modify RX function

V1.2 01/14/2005 Add Early transmit mode

V1.3 03/02/2005 Support kernel 2.6

v1.33 06/08/2005 #define DM9KS_MDRAL 0xf4

#define DM9KS_MDRAH 0xf5

V2.00 01/10/2005 Spenser

- Modification for PXA270 MAINSTONE.

- Modified dmfe_tx_done().

- Add dmfe_timeout().

V2.01 10/07/2005 Modified dmfe_timer()

Dected network speed 10/100M

V2.02 10/12/2005 Use link change to chage db->Speed

dmfe_open() wait for Link OK

V2.03 11/22/2005 Power-off and Power-on PHY in dmfe_init() support IOL

*/

#if defined(MODVERSIONS)

#include

#endif

#include

#include

#include

#include

#include

#include

#include

#include

#include

#include

#include

#include

#ifdef CONFIG_ARCH_MAINSTONE

#include

#include

#include

#endif

/* Board/System/Debug information/definition ---------------- */

#define DM9KS_ID 0x90000A46

#define DM9010_ID 0x90100A46

/*-------register name-----------------------*/

#define DM9KS_NCR 0x00 /* Network control Reg.*/

#define DM9KS_NSR 0x01 /* Network Status Reg.*/

#define DM9KS_TCR 0x02 /* TX control Reg.*/

#define DM9KS_RXCR 0x05 /* RX control Reg.*/

#define DM9KS_BPTR 0x08

#define DM9KS_EPCR 0x0b

#define DM9KS_EPAR 0x0c

#define DM9KS_EPDRL 0x0d

#define DM9KS_EPDRH 0x0e

#define DM9KS_GPR 0x1f /* General purpose register */

#define DM9KS_TCR2 0x2d

#define DM9KS_SMCR 0x2f /* Special Mode Control Reg.*/

#define DM9KS_ETXCSR 0x30 /* Early Transmit control/status Reg.*/

#define DM9KS_TCCR 0x31 /* Checksum cntrol Reg. */

#define DM9KS_RCSR 0x32 /* Receive Checksum status Reg.*/

#define DM9KS_MRCMDX 0xf0

#define DM9KS_MRCMD 0xf2

#define DM9KS_MDRAL 0xf4

#define DM9KS_MDRAH 0xf5

#define DM9KS_MWCMD 0xf8

#define DM9KS_TXPLL 0xfc

#define DM9KS_TXPLH 0xfd

#define DM9KS_ISR 0xfe

#define DM9KS_IMR 0xff

/*---------------------------------------------*/

#define DM9KS_REG05 0x30 /* SKIP_CRC/SKIP_LONG */

#define DM9KS_REGFF 0xA3 /* IMR */

#define DM9KS_DISINTR 0x80

#define DM9KS_PHY 0x40 /* PHY address 0x01 */

#define DM9KS_PKT_RDY 0x01 /* Packet ready to receive */

/* Added for PXA of MAINSTONE */

#ifdef CONFIG_ARCH_MAINSTONE

#include

#define DM9KS_MIN_IO (MST_ETH_PHYS + 0x300)

#define DM9KS_MAX_IO (MST_ETH_PHYS + 0x370)

#define DM9K_IRQ MAINSTONE_IRQ(3)

#else

#define DM9KS_MIN_IO 0x300

#define DM9KS_MAX_IO 0x370

#define DM9K_IRQ 3

#endif

#define DM9KS_VID_L 0x28

#define DM9KS_VID_H 0x29

#define DM9KS_PID_L 0x2A

#define DM9KS_PID_H 0x2B

#define DM9KS_RX_INTR 0x01

#define DM9KS_TX_INTR 0x02

#define DM9KS_LINK_INTR 0x20

#define DM9KS_DWORD_MODE 1

#define DM9KS_BYTE_MODE 2

#define DM9KS_WORD_MODE 0

#define TRUE 1

#define FALSE 0

/* Number of continuous Rx packets */

#define CONT_RX_PKT_CNT 10

#define DMFE_TIMER_WUT jiffies+(HZ*5) /* timer wakeup time : 5 second */

#if defined(DM9KS_DEBUG)

#define DMFE_DBUG(dbug_now, msg, vaule)

if (dmfe_debug||dbug_now) printk(KERN_ERR dmfe: %s %xn, msg, vaule)pid控制相关文章:pid控制原理

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